Samsung Launches BV-NAND Technology with 58% Increased Storage Density

Samsung Electronics unveiled its V10 Bonding V-NAND, or BV-NAND prototype, at the Future Storage and Memory Conference in Santa Clara, California. This chip features over 400 layers and employs a new wafer bonding architecture, achieving approximately a 58% increase in storage density compared to the previous generation V9 NAND. It also enhances read, write, and input/output performance to meet the demands of artificial intelligence systems for high-capacity, energy-efficient storage. Additionally, Samsung showcased the industry's first zHBM and zNAND-O architecture concept models, which utilize vertically stacked memory cells to shorten data transmission distances and improve bandwidth and energy efficiency. Samsung stated that its wafer bonding technology is expected to achieve more than ten times the storage density of traditional HBM5 memory, with a threefold increase in energy efficiency and a reduction in thermal resistance by more than half.

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